抜粋
As the technology of semiconductor continues to develop, hundreds of cores will be deployed on a signal die in the future Chip-Multiprocessors (CMPs) design. So Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide high performance. The network performance depends critically on the performance of routing algorithm. This paper proposes a novel adaptive routing in 3D NoC which can solve congestion not only in the intra-layers but also in inter-layers. Simulation results show that our proposed method significantly achieves the performance improvement compared with other transitional routing algorithms.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | IEEE Region 10 Annual International Conference, Proceedings/TENCON |
| 出版者 | Institute of Electrical and Electronics Engineers Inc. |
| 巻 | 2016-January |
| ISBN（印刷物） | 9781479986415 |
| DOI | |
| 出版物ステータス | Published - 2016 1 5 |
| イベント | 35th IEEE Region 10 Conference, TENCON 2015 - Macau, Macao 継続期間: 2015 11 1 → 2015 11 4 |
Other
| Other | 35th IEEE Region 10 Conference, TENCON 2015 |
|---|---|
| 国 | Macao |
| 市 | Macau |
| 期間 | 15/11/1 → 15/11/4 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications
フィンガープリント A performance enhanced adaptive routing algorithm for 3D Network-on-Chips' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。
これを引用
Zeng, L., Pan, T., Jiang, X., & Watanabe, T. (2016). A performance enhanced adaptive routing algorithm for 3D Network-on-Chips. ： IEEE Region 10 Annual International Conference, Proceedings/TENCON (巻 2016-January). [7373036] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TENCON.2015.7373036