A performance enhanced adaptive routing algorithm for 3D Network-on-Chips

Lian Zeng; Tieyuan Pan; Xin Jiang; Takahiro Watanabe

doi:10.1109/TENCON.2015.7373036

A performance enhanced adaptive routing algorithm for 3D Network-on-Chips

Lian Zeng, Tieyuan Pan, Xin Jiang, Takahiro Watanabe

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

As the technology of semiconductor continues to develop, hundreds of cores will be deployed on a signal die in the future Chip-Multiprocessors (CMPs) design. So Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide high performance. The network performance depends critically on the performance of routing algorithm. This paper proposes a novel adaptive routing in 3D NoC which can solve congestion not only in the intra-layers but also in inter-layers. Simulation results show that our proposed method significantly achieves the performance improvement compared with other transitional routing algorithms.

本文言語	English
ホスト出版物のタイトル	IEEE Region 10 Annual International Conference, Proceedings/TENCON
出版社	Institute of Electrical and Electronics Engineers Inc.
巻	2016-January
ISBN（印刷版）	9781479986415
DOI	https://doi.org/10.1109/TENCON.2015.7373036
出版ステータス	Published - 2016 1月 5
イベント	35th IEEE Region 10 Conference, TENCON 2015 - Macau, Macao 継続期間: 2015 11月 1 → 2015 11月 4

Other

Other	35th IEEE Region 10 Conference, TENCON 2015
国/地域	Macao
City	Macau
Period	15/11/1 → 15/11/4

ASJC Scopus subject areas

電子工学および電気工学
コンピュータサイエンスの応用

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10.1109/TENCON.2015.7373036

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引用スタイル

Zeng, L, Pan, T, Jiang, X & Watanabe, T 2016, A performance enhanced adaptive routing algorithm for 3D Network-on-Chips. in IEEE Region 10 Annual International Conference, Proceedings/TENCON. vol. 2016-January, 7373036, Institute of Electrical and Electronics Engineers Inc., 35th IEEE Region 10 Conference, TENCON 2015, Macau, Macao, 15/11/1. https://doi.org/10.1109/TENCON.2015.7373036

@inproceedings{1447edea47fc4f27bd450d1de291f11c,

title = "A performance enhanced adaptive routing algorithm for 3D Network-on-Chips",

abstract = "As the technology of semiconductor continues to develop, hundreds of cores will be deployed on a signal die in the future Chip-Multiprocessors (CMPs) design. So Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide high performance. The network performance depends critically on the performance of routing algorithm. This paper proposes a novel adaptive routing in 3D NoC which can solve congestion not only in the intra-layers but also in inter-layers. Simulation results show that our proposed method significantly achieves the performance improvement compared with other transitional routing algorithms.",

keywords = "3D network-on-chip, Adaptive routing, congestion-balance, path diversity",

author = "Lian Zeng and Tieyuan Pan and Xin Jiang and Takahiro Watanabe",

year = "2016",

month = jan,

day = "5",

doi = "10.1109/TENCON.2015.7373036",

language = "English",

isbn = "9781479986415",

volume = "2016-January",

booktitle = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "35th IEEE Region 10 Conference, TENCON 2015 ; Conference date: 01-11-2015 Through 04-11-2015",

}

TY - GEN

T1 - A performance enhanced adaptive routing algorithm for 3D Network-on-Chips

AU - Zeng, Lian

AU - Pan, Tieyuan

AU - Jiang, Xin

AU - Watanabe, Takahiro

PY - 2016/1/5

Y1 - 2016/1/5

N2 - As the technology of semiconductor continues to develop, hundreds of cores will be deployed on a signal die in the future Chip-Multiprocessors (CMPs) design. So Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide high performance. The network performance depends critically on the performance of routing algorithm. This paper proposes a novel adaptive routing in 3D NoC which can solve congestion not only in the intra-layers but also in inter-layers. Simulation results show that our proposed method significantly achieves the performance improvement compared with other transitional routing algorithms.

AB - As the technology of semiconductor continues to develop, hundreds of cores will be deployed on a signal die in the future Chip-Multiprocessors (CMPs) design. So Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide high performance. The network performance depends critically on the performance of routing algorithm. This paper proposes a novel adaptive routing in 3D NoC which can solve congestion not only in the intra-layers but also in inter-layers. Simulation results show that our proposed method significantly achieves the performance improvement compared with other transitional routing algorithms.

KW - 3D network-on-chip

KW - Adaptive routing

KW - congestion-balance

KW - path diversity

UR - http://www.scopus.com/inward/record.url?scp=84962144473&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84962144473&partnerID=8YFLogxK

U2 - 10.1109/TENCON.2015.7373036

DO - 10.1109/TENCON.2015.7373036

M3 - Conference contribution

AN - SCOPUS:84962144473

SN - 9781479986415

VL - 2016-January

BT - IEEE Region 10 Annual International Conference, Proceedings/TENCON

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 35th IEEE Region 10 Conference, TENCON 2015

Y2 - 1 November 2015 through 4 November 2015

ER -

A performance enhanced adaptive routing algorithm for 3D Network-on-Chips

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