A performance enhanced dual-switch Network-on-Chip architecture

Lian Zeng, Takahiro Watanabe

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

本文言語English
ホスト出版物のタイトル20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ページ69-74
ページ数6
ISBN(印刷版)9781479977925
DOI
出版ステータスPublished - 2015 3 11
イベント2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
継続期間: 2015 1 192015 1 22

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period15/1/1915/1/22

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

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