A performance enhanced dual-switch network-on-chip architecture

Lian Zeng, Xin Jiang, Takahiro Watanabe

研究成果: Article査読

抄録

With rapid progress in semiconductor technology, Network-on-Chip (NoC) becomes an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. The delay of router and packets contention can significantly affect network latency and throughput. As the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing DSA design, we can make utmost use of idle output ports to reduce packets contention delay, meanwhile, without increasing router delay. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power and area overhead.

本文言語English
ページ(範囲)85-94
ページ数10
ジャーナルIPSJ Transactions on System LSI Design Methodology
8
DOI
出版ステータスPublished - 2015 2 1

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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