A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC

Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

A fine-grain scalable parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, m×16 process elements (PE) are scheduled to work in parallel and fully utilized. The basic extension grain is one process element group (PEG), which accounts for 16 PE and 8.5K gates. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.

元の言語English
ホスト出版物のタイトル25th PCS Proceedings
ホスト出版物のサブタイトルPicture Coding Symposium 2006, PCS2006
出版物ステータスPublished - 2006 12 1
イベント25th PCS: Picture Coding Symposium 2006, PCS2006 - Beijing, China
継続期間: 2006 4 242006 4 26

出版物シリーズ

名前25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006
2006

Conference

Conference25th PCS: Picture Coding Symposium 2006, PCS2006
China
Beijing
期間06/4/2406/4/26

ASJC Scopus subject areas

  • Engineering(all)

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  • これを引用

    Liu, Z., Song, Y., Ikenaga, T., & Goto, S. (2006). A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC. : 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006 (25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006; 巻数 2006).