A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard

Yibo Fan, Yixuan Zeng, Heming Sun, Jiro Katto, Xiaoyang Zeng

研究成果: Article査読

1 被引用数 (Scopus)

抄録

For the next-generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified 32× 32 block-based transform architecture for the VVC standard that enables 2D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. It mainly gives three contributions: 1) The N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the minimal adder-oriented computational units. 2) The storage of the asymmetric transform units can be realized in the dual-port SRAM-based transpose memory. 3) The pipelined 2D transformations of mixed block sizes are achieved with the throughput rate of 32 samples per cycle. The synthesis results indicate that this architecture can reduce area by up to 73.1% compared with other state-of-the-art works. Moreover, power saving ranging from 4.9% to 9.9% can be achieved. Regarding the transpose memory, at least 21.9% of the area can be saved by using SRAM.

本文言語English
論文番号8794833
ページ(範囲)3289-3295
ページ数7
ジャーナルIEEE Transactions on Circuits and Systems for Video Technology
30
9
DOI
出版ステータスPublished - 2020 9

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

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