A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability

研究成果: Conference contribution

抄録

A power-efficient single node upset hardened latch design with in-situ error detection capability, EDSL, is proposed in this paper for reliability improvement against soft errors. Our simulation results show that the proposed EDSL design can not only recover from any incurred single node upset, but also provide in-situ error detection capability when the latch output is upset. When compared with state-of-the-art error-detection-based and SNU resilient designs, the proposed EDSL latch can achieve up to 72.25% and 79.74% reduction of power-delay-product respectively, which clearly shows the effectiveness of the proposed method.

本文言語English
ホスト出版物のタイトルProceedings - PrimeAsia 2019
ホスト出版物のサブタイトル2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Innovative CAS Towards Sustainable Energy and Technology Disruption
出版社IEEE Computer Society
ページ53-56
ページ数4
ISBN(電子版)9781728130552
DOI
出版ステータスPublished - 2019 11
イベント2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2019 - Bangkok, Thailand
継続期間: 2019 11 112019 11 14

出版物シリーズ

名前Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
2019-November
ISSN(印刷版)2159-2144
ISSN(電子版)2159-2160

Conference

Conference2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2019
国/地域Thailand
CityBangkok
Period19/11/1119/11/14

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 教育

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