A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

H. Koike, T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi

研究成果: Conference contribution

20 被引用数 (Scopus)

抄録

We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.

本文言語English
ホスト出版物のタイトルProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
ページ317-320
ページ数4
DOI
出版ステータスPublished - 2013 12 1
外部発表はい
イベント2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
継続期間: 2013 11 112013 11 13

出版物シリーズ

名前Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Conference

Conference2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
CountrySingapore
CitySingapore
Period13/11/1113/11/13

ASJC Scopus subject areas

  • Hardware and Architecture

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