A power-saved 1Gbps irregular LDPC decoder based on simplified min-sum algorithm

Qi Wang, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

In this paper we proposed a fully-parallel irregular LDPC decoder which uses only registers to store the temporary intrinsic messages. Our decoder adopts a simplified min-sum algorithm to reduce the hardware implementation complexity and area, and due to the factor modification we achieve a negligible performance loss compared with the general min-sum algorithm. Considering reducing the power consumption, we also propose a power-saved strategy according to which the message evolution will halt as the parity-check condition is satisfied. This strategy will save us higher than 50% power under good channel condition. The synthesis result in 0.18μm CMOS technology shows our decoder for (648,540) irregular LDPC code achieves high throughput (1 Gbps) with 9.0ns latency.

本文言語English
ホスト出版物のタイトル2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOI
出版ステータスPublished - 2007 9 28
イベント2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan, Province of China
継続期間: 2007 4 252007 4 27

出版物シリーズ

名前2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
CountryTaiwan, Province of China
CityHsinchu
Period07/4/2507/4/27

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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