A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a process-variation-aware low-latency and multi-scenario high-level synthesis algorithm targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.

元の言語English
ホスト出版物のタイトルProceedings - 28th IEEE International System on Chip Conference, SOCC 2015
編集者Thomas Buchner, Danella Zhao, Karan Bhatia, Ramalingam Sridhar
出版者IEEE Computer Society
ページ7-12
ページ数6
ISBN(電子版)9781467390934
DOI
出版物ステータスPublished - 2016 2 12
イベント28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
継続期間: 2015 9 82015 9 11

出版物シリーズ

名前International System on Chip Conference
2016-February
ISSN(印刷物)2164-1676
ISSN(電子版)2164-1706

Other

Other28th IEEE International System on Chip Conference, SOCC 2015
China
Beijing
期間15/9/815/9/11

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • これを引用

    Igawa, K., Shi, Y., Yanagisawa, M., & Togawa, N. (2016). A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. : T. Buchner, D. Zhao, K. Bhatia, & R. Sridhar (版), Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015 (pp. 7-12). [7406898] (International System on Chip Conference; 巻数 2016-February). IEEE Computer Society. https://doi.org/10.1109/SOCC.2015.7406898