A real-time 64-monosyllable recognition LSI with learning mechanism

K. Nakamura, Qiang Zhu, S. Maruoka, T. Horiyama, S. Kimura, K. Watanabe

研究成果: Conference contribution

抄録

In the paper, a real-time 64-mono-syllable recognition LSI is presented. The LSI accepts 11.6 ms speech frame and outputs a 6-bit symbol-code for each frame by the end of the next frame in a pipelining manner. The recognition method is based on the Hidden Markov Model (HMM) and is speaker-independent. An on-chip learning mechanism has also been designed, but the circuit is off-chip for the present implementation because of the restriction of LSI area. The LSI is fabricated by VDEC Rohm with a 0.6 μm CMOS process on a 4.5 mmx4.5 mm chip.

本文言語English
ホスト出版物のタイトルProceedings of the ASP-DAC 2001
ホスト出版物のサブタイトルAsia and South Pacific Design Automation Conference 2001
出版社Institute of Electrical and Electronics Engineers Inc.
ページ31-32
ページ数2
ISBN(電子版)0780366336
DOI
出版ステータスPublished - 2001
外部発表はい
イベントAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
継続期間: 2001 1 302001 2 2

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
国/地域Japan
CityYokohama
Period01/1/3001/2/2

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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