A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.

本文言語English
ホスト出版物のタイトルProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
ページ152a
DOI
出版ステータスPublished - 2005 12 1
イベント19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO, United States
継続期間: 2005 4 42005 4 8

出版物シリーズ

名前Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
2005

Conference

Conference19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
国/地域United States
CityDenver, CO
Period05/4/405/4/8

ASJC Scopus subject areas

  • 工学(全般)

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