A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Yutaka Arima; Mitsuhiro Murasaki; Tsuyoshi Yamada; Atsushi Maeda; Hirofumi Shinohara

doi:10.1109/4.173115

A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara

研究成果: Article

25 被引用数 (Scopus)

抄録

This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.

本文言語	English
ページ（範囲）	1854-1861
ページ数	8
ジャーナル	IEEE Journal of Solid-State Circuits
巻	27
号	12
DOI	https://doi.org/10.1109/4.173115
出版ステータス	Published - 1992 12
外部発表	はい

ASJC Scopus subject areas

Electrical and Electronic Engineering

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引用スタイル

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