A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atushi Maeda, Hirofumi Shinohara

研究成果: Article

25 引用 (Scopus)

抄録

An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40,000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.

元の言語English
ページ（範囲）1854-1861
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
巻27
発行部数12
DOI
出版物ステータスPublished - 1992 12
外部発表Yes

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Analog storage
LSI circuits
Neurons
Neural networks
Metals

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses. / Arima, Yutaka; Murasaki, Mitsuhiro; Yamada, Tsuyoshi; Maeda, Atushi; Shinohara, Hirofumi.

：: IEEE Journal of Solid-State Circuits, 巻 27, 番号 12, 12.1992, p. 1854-1861.

研究成果: Article

Arima, Y, Murasaki, M, Yamada, T, Maeda, A & Shinohara, H 1992, 'A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses', IEEE Journal of Solid-State Circuits, 巻. 27, 番号 12, pp. 1854-1861. https://doi.org/10.1109/4.173115
Arima Y, Murasaki M, Yamada T, Maeda A, Shinohara H. A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses. IEEE Journal of Solid-State Circuits. 1992 12;27(12):1854-1861. https://doi.org/10.1109/4.173115
Arima, Yutaka ; Murasaki, Mitsuhiro ; Yamada, Tsuyoshi ; Maeda, Atushi ; Shinohara, Hirofumi. / A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses. ：: IEEE Journal of Solid-State Circuits. 1992 ; 巻 27, 番号 12. pp. 1854-1861.
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