抜粋
This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 1854-1861 |
| ページ数 | 8 |
| ジャーナル | IEEE Journal of Solid-State Circuits |
| 巻 | 27 |
| 発行部数 | 12 |
| DOI | |
| 出版物ステータス | Published - 1992 12 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
フィンガープリント A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。
これを引用
Arima, Y., Murasaki, M., Yamada, T., Maeda, A., & Shinohara, H. (1992). A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses. IEEE Journal of Solid-State Circuits, 27(12), 1854-1861. https://doi.org/10.1109/4.173115