抄録
This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.
本文言語 | English |
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ページ(範囲) | 1854-1861 |
ページ数 | 8 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 27 |
号 | 12 |
DOI | |
出版ステータス | Published - 1992 12月 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学