A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara

研究成果: Article

25 引用 (Scopus)

抜粋

This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.

元の言語English
ページ(範囲)1854-1861
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
27
発行部数12
DOI
出版物ステータスPublished - 1992 12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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