A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Yutaka Arima; Mitsuhiro Murasaki; Tsuyoshi Yamada; Atsushi Maeda; Hirofumi Shinohara

doi:10.1109/4.173115

A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara

研究成果: Article › 査読

27 被引用数 (Scopus)

抄録

This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.

本文言語	English
ページ（範囲）	1854-1861
ページ数	8
ジャーナル	IEEE Journal of Solid-State Circuits
巻	27
号	12
DOI	https://doi.org/10.1109/4.173115
出版ステータス	Published - 1992 12月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/4.173115

他のファイルとリンク

引用スタイル

@article{3902789e1d654fcf806b62ed57b3b106,

title = "A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses",

abstract = "This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.",

author = "Yutaka Arima and Mitsuhiro Murasaki and Tsuyoshi Yamada and Atsushi Maeda and Hirofumi Shinohara",

year = "1992",

month = dec,

doi = "10.1109/4.173115",

language = "English",

volume = "27",

pages = "1854--1861",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

AU - Arima, Yutaka

AU - Murasaki, Mitsuhiro

AU - Yamada, Tsuyoshi

AU - Maeda, Atsushi

AU - Shinohara, Hirofumi

PY - 1992/12

Y1 - 1992/12

N2 - This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.

AB - This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.

UR - http://www.scopus.com/inward/record.url?scp=0026987728&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026987728&partnerID=8YFLogxK

U2 - 10.1109/4.173115

DO - 10.1109/4.173115

M3 - Article

AN - SCOPUS:0026987728

VL - 27

SP - 1854

EP - 1861

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 12

ER -

A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

抄録

ASJC Scopus subject areas

文献へのアクセス

他のファイルとリンク

フィンガープリント

引用スタイル