抄録
An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40,000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.
元の言語 | English |
---|---|
ページ(範囲) | 1854-1861 |
ページ数 | 8 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 27 |
発行部数 | 12 |
DOI | |
出版物ステータス | Published - 1992 12 |
外部発表 | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
これを引用
A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses. / Arima, Yutaka; Murasaki, Mitsuhiro; Yamada, Tsuyoshi; Maeda, Atushi; Shinohara, Hirofumi.
:: IEEE Journal of Solid-State Circuits, 巻 27, 番号 12, 12.1992, p. 1854-1861.研究成果: Article
}
TY - JOUR
T1 - A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses
AU - Arima, Yutaka
AU - Murasaki, Mitsuhiro
AU - Yamada, Tsuyoshi
AU - Maeda, Atushi
AU - Shinohara, Hirofumi
PY - 1992/12
Y1 - 1992/12
N2 - An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40,000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.
AB - An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40,000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.
UR - http://www.scopus.com/inward/record.url?scp=0026987728&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0026987728&partnerID=8YFLogxK
U2 - 10.1109/4.173115
DO - 10.1109/4.173115
M3 - Article
AN - SCOPUS:0026987728
VL - 27
SP - 1854
EP - 1861
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 12
ER -