A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atushi Maeda, Hirofumi Shinohara

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Describes a self-learning neural network chip with refresh on-chip analog synaptic weight storage. The chip integrates 400 neurons and 40000 synapses with 0.8μm double poly-Si double metal CMOS technology. Refresh time is less than 300 mu s. The chip retains learned information by repeating refresh at 100 ms intervals. The proposed refresh method is based on the decision made by a subnetwork. The subnetwork learns if the settling states of the main network should be memorized, retains the weights until they are relearned, and stores a 4-b representation of subnetwork weights in a counter. The main network is refreshed according to the output of the subnetwork.

本文言語English
ホスト出版物のタイトルDigest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
出版社Institute of Electrical and Electronics Engineers Inc.
ページ132-133
ページ数2
ISBN(電子版)0780305736
DOI
出版ステータスPublished - 1992 1 1
外部発表はい
イベント39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States
継続期間: 1992 2 191992 2 21

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
1992-February
ISSN(印刷版)0193-6530

Conference

Conference39th IEEE International Solid-State Circuits Conference, ISSCC 1992
CountryUnited States
CitySan Francisco
Period92/2/1992/2/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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