A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Nishimura Yasumasa, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

研究成果: Article

抜粋

This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

元の言語English
ページ(範囲)909-913
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
20
発行部数5
DOI
出版物ステータスPublished - 1985
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Kumanoya, M., Fujishima, K., Miyatake, H., Yasumasa, N., Saito, K., Matsukawa, T., Yoshihara, T., & Nakano, T. (1985). A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode. IEEE Journal of Solid-State Circuits, 20(5), 909-913. https://doi.org/10.1109/JSSC.1985.1052414