A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices

Yuuichi Hirano*, Mikio Tsujiuchi, Kozo Ishikawa, Hirofumi Shinohara, Takashi Terada, Yukio Maki, Toshiaki Iwamatsu, Katsumi Eikyu, Tetsuya Uchida, Shigeki Obayashi, Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Takashi Ipposhi, Hidekazu Oda, Yasuo Inoue

*この研究の対応する著者

研究成果: Conference article査読

8 被引用数 (Scopus)

抄録

This paper presents that Advanced Actively Body-bias Controlled (Advanced ABC) technology contributes to enhancing operation margins of SRAMs. Significant enhancement of Static Noise Margin (SNM) is successfully realized by using a body bias of load transistors while suppressing threshold-voltage variations for the first time. It is demonstrated that the write and read margins of 65nm-node SOI SRAMs are improved by the Advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32nm and 49% for 22nm node. It is summarized that this technology is one of countermeasures for emerging generations.

本文言語English
論文番号4339734
ページ(範囲)78-79
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
DOI
出版ステータスPublished - 2007 12月 1
外部発表はい
イベント2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
継続期間: 2007 6月 122007 6月 14

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル