This paper presents a logic synthesis system based on a combined rule-based and algorithmic approach, where not only tables for transformation are described as rules, but also a two level logic minimization algorithm is registered as one of the rules. A rule interpreter fires these rules using an effective branch and bound technique. Physical constraints such as longest path lengths between registers, fan-in/out and polarity are checked whenever each rule is applied. The system was implemented in the C language on a SUN workstation and has been applied for actual circuits used in production. The results show that the system generates solutions very close to the manual implementation. They also show that the system with the logic minimization algorithm was skipped.
ASJC Scopus subject areas
- コンピュータ サイエンスの応用