TY - JOUR
T1 - A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition
AU - Togawa, Nozomu
AU - Tachikake, Koichi
AU - Miyaoka, Yuichiro
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2005/7
Y1 - 2005/7
N2 - This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.
AB - This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.
KW - Hardware/software cosynthesis
KW - Instruction set synthesis
KW - Packed SIMD-type functional unit
KW - Packed SIMD-type instruction
KW - Processor synthesis
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U2 - 10.1093/ietisy/e88-d.7.1340
DO - 10.1093/ietisy/e88-d.7.1340
M3 - Article
AN - SCOPUS:26044471479
VL - E88-D
SP - 1340
EP - 1349
JO - IEICE Transactions on Information and Systems
JF - IEICE Transactions on Information and Systems
SN - 0916-8532
IS - 7
ER -