A simultaneous placement and global routing algorithm for FPGAs with power optimization

Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki

研究成果: Article査読

抄録

This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to nets with high switching probabilities and attempts to assign the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

本文言語English
ページ(範囲)99-112
ページ数14
ジャーナルJournal of Circuits, Systems and Computers
9
1-2
DOI
出版ステータスPublished - 1999 1 1

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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