A sophisticated routing algorithm in 3D NoC with fixed TSVs for low energy and latency

Xin Jiang, Lian Zeng, Takahiro Watanabe

研究成果: Article査読

4 被引用数 (Scopus)

抄録

With rapid progress in Integrated Circuit technologies, Three-Dimensional Network-on-Chips (3DNoCs) have become a promising solution for achieving low latency and low power. Under the constraint of the TSV number used in 3DNoCs, designing a proper routing algorithm with fewer TSVs is a critical problem for network performance improvement. In this work, we design a novel fully adaptive routing algorithm in 3D NoC. The algorithm consists of two parts: one is a vertical node assignment in inter-layer routing, which is a TSV selection scheme in a limited quantity of TSVs in the NoC architecture, and the other is a 2D fully adaptive routing algorithm in intra-layer routing, which combines the optimization of routing distance, network traffic condition and diversity of the path selection. Simulation results show that our proposed routing algorithm can achieve lower latency and energy consumption compared with other traditional routing algorithms.

本文言語English
ページ(範囲)101-109
ページ数9
ジャーナルIPSJ Transactions on System LSI Design Methodology
7
DOI
出版ステータスPublished - 2014

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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