A sorting-based architecture of finding the first two minimum values for LDPC decoding

Qian Xie, Zhixiang Chen, Xiao Peng, Satoshi Goto

研究成果: Conference contribution

5 引用 (Scopus)

抜粋

This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.

元の言語English
ホスト出版物のタイトルProceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
ページ95-98
ページ数4
DOI
出版物ステータスPublished - 2011
イベント2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 - Penang
継続期間: 2011 3 42011 3 6

Other

Other2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
Penang
期間11/3/411/3/6

ASJC Scopus subject areas

  • Signal Processing

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  • これを引用

    Xie, Q., Chen, Z., Peng, X., & Goto, S. (2011). A sorting-based architecture of finding the first two minimum values for LDPC decoding. : Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 (pp. 95-98). [5759850] https://doi.org/10.1109/CSPA.2011.5759850