A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara

doi:10.1093/ietele/e88-c.10.2020

A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

Akira Yamazaki^*, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Article › 査読

1 被引用数 (Scopus)

抄録

The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

本文言語	English
ページ（範囲）	2020-2026
ページ数	7
ジャーナル	IEICE Transactions on Electronics
巻	E88-C
号	10
DOI	https://doi.org/10.1093/ietele/e88-c.10.2020
出版ステータス	Published - 2005 10月

ASJC Scopus subject areas

電子工学および電気工学

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10.1093/ietele/e88-c.10.2020

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引用スタイル

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AU - Yamazaki, Akira

AU - Morishita, Fukashi

AU - Watanabe, Naoya

AU - Amano, Teruhiko

AU - Haraguchi, Masaru

AU - Noda, Hideyuki

AU - Hachisuka, Atsushi

AU - Dosaka, Katsumi

AU - Arimoto, Kazutami

AU - Wake, Setsuo

AU - Ozaki, Hideyuki

AU - Yoshihara, Tsutomu

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N2 - The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

AB - The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

KW - DRAM

KW - Embedded memory

KW - Low voltage

KW - System on chip

KW - Voltage margin

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A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

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