A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

Akira Yamazaki*, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

*この研究の対応する著者

    研究成果: Article査読

    1 被引用数 (Scopus)

    抄録

    The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

    本文言語English
    ページ(範囲)2020-2026
    ページ数7
    ジャーナルIEICE Transactions on Electronics
    E88-C
    10
    DOI
    出版ステータスPublished - 2005 10月

    ASJC Scopus subject areas

    • 電子工学および電気工学

    フィンガープリント

    「A study of sense-voltage margins in low-voltage-operating embedded DRAM macros」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル