A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation

    研究成果: Conference contribution

    抄録

    Recently, high-functioning hardware devices such as smart TVs and smart phones have been widely used in our daily lives. To keep up with the rapid advance of these high technologies, reconfigurable hardware devices such as FP-GAs (Field Programmable Gate Arrays) have been used in final products. Under the circumstances, the risks that mal-functions may be inserted into hardware devices have arisen. The malfunctions inserted into hardware devices are known as hardware Trojans. How to detect them becomes serious concern in hardware production. In this paper, we design a Trojan-infected cryptographic circuit as well as a Trojan-invalidating circuit, and implement them on an FPGA board. To begin with, we design an AES cryptographic circuit. Secondly, we insert a hardware Trojan into the AES cryptographic circuit. Finally, we design a Trojan-invalidating circuit and insert it into a suspicious Trojan net in the Trojan-infected cryptographic circuit. After that, we implement the circuits into an FPGA board. The experimental results demonstrate that the Trojan-invalidating circuit adequately deactivate the suspicious Trojan net in the Trojan-infected cryptographic circuit.

    元の言語English
    ホスト出版物のタイトル2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
    出版者Institute of Electrical and Electronics Engineers Inc.
    2018-May
    ISBN(電子版)9781538648810
    DOI
    出版物ステータスPublished - 2018 4 26
    イベント2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
    継続期間: 2018 5 272018 5 30

    Other

    Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
    Italy
    Florence
    期間18/5/2718/5/30

    Fingerprint

    Field programmable gate arrays (FPGA)
    Networks (circuits)
    Hardware
    Reconfigurable hardware

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    これを引用

    Hasegawa, K., Yanagisawa, M., & Togawa, N. (2018). A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. : 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings (巻 2018-May). [8351058] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351058

    A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. / Hasegawa, Kento; Yanagisawa, Masao; Togawa, Nozomu.

    2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. 巻 2018-May Institute of Electrical and Electronics Engineers Inc., 2018. 8351058.

    研究成果: Conference contribution

    Hasegawa, K, Yanagisawa, M & Togawa, N 2018, A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. : 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. 巻. 2018-May, 8351058, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 18/5/27. https://doi.org/10.1109/ISCAS.2018.8351058
    Hasegawa K, Yanagisawa M, Togawa N. A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. : 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. 巻 2018-May. Institute of Electrical and Electronics Engineers Inc. 2018. 8351058 https://doi.org/10.1109/ISCAS.2018.8351058
    Hasegawa, Kento ; Yanagisawa, Masao ; Togawa, Nozomu. / A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. 巻 2018-May Institute of Electrical and Electronics Engineers Inc., 2018.
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