A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation

研究成果: Conference contribution

抄録

Recently, high-functioning hardware devices such as smart TVs and smart phones have been widely used in our daily lives. To keep up with the rapid advance of these high technologies, reconfigurable hardware devices such as FP-GAs (Field Programmable Gate Arrays) have been used in final products. Under the circumstances, the risks that mal-functions may be inserted into hardware devices have arisen. The malfunctions inserted into hardware devices are known as hardware Trojans. How to detect them becomes serious concern in hardware production. In this paper, we design a Trojan-infected cryptographic circuit as well as a Trojan-invalidating circuit, and implement them on an FPGA board. To begin with, we design an AES cryptographic circuit. Secondly, we insert a hardware Trojan into the AES cryptographic circuit. Finally, we design a Trojan-invalidating circuit and insert it into a suspicious Trojan net in the Trojan-infected cryptographic circuit. After that, we implement the circuits into an FPGA board. The experimental results demonstrate that the Trojan-invalidating circuit adequately deactivate the suspicious Trojan net in the Trojan-infected cryptographic circuit.

本文言語English
ホスト出版物のタイトル2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781538648810
DOI
出版ステータスPublished - 2018 4 26
イベント2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
継続期間: 2018 5 272018 5 30

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
2018-May
ISSN(印刷版)0271-4310

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period18/5/2718/5/30

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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