A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

13 被引用数 (Scopus)

抄録

The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k gates@200MHz, with TSMC CMOS 0.18m technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

本文言語English
ホスト出版物のタイトルGLSVLSI'07
ホスト出版物のサブタイトルProceedings of the 2007 ACM Great Lakes Symposium on VLSI
ページ20-24
ページ数5
DOI
出版ステータスPublished - 2007 10 1
イベント17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy
継続期間: 2007 3 112007 3 13

出版物シリーズ

名前Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference17th Great Lakes Symposium on VLSI, GLSVLSI'07
CountryItaly
CityStresa-Lago Maggiore
Period07/3/1107/3/13

ASJC Scopus subject areas

  • Engineering(all)

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