A VLSI architecture for motion compensation interpolation in H.264/AVC

Yang Song, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

研究成果: Conference contribution

11 引用 (Scopus)

抜粋

A VLSI architecture for motion estimation/compensation interpolation in H.264/AVC is presented in this paper. Compared with previous work, this architecture has following characteristics: First, it supports all block modes and fractional samples adopted in H.264/AVC standard. Second, no extra initiation and finalization time is required, which enhances the system performance. Third, a pipelined finite impulse filter (FIR) is used to replace the traditional adder tree, which increases the system clock frequency. Because this design applies full pipelined architecture, it can generate one half sample in every cycle and eight quarter samples in every nine cycles with little pipeline latency. In fact, this architecture with minor revision could be adopted in MPEG-4 and other video coding standards. The design is implemented with TSMC 0.18μm CMOS technology. The core area is 0.577×0.661 mm 2 and frequency is 274MHz in typical condition (1.8V, 25°C).

元の言語English
ホスト出版物のタイトルASICON 2005
ホスト出版物のサブタイトル2005 6th International Conference on ASIC, Proceedings
ページ262-265
ページ数4
出版物ステータスPublished - 2005 12 1
イベントASICON 2005: 2005 6th International Conference on ASIC - Shanghai, China
継続期間: 2005 10 242005 10 27

出版物シリーズ

名前ASICON 2005: 2005 6th International Conference on ASIC, Proceedings
1

Conference

ConferenceASICON 2005: 2005 6th International Conference on ASIC
China
Shanghai
期間05/10/2405/10/27

ASJC Scopus subject areas

  • Engineering(all)

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  • これを引用

    Song, Y., Liu, Z., Goto, S., & Ikenaga, T. (2005). A VLSI architecture for motion compensation interpolation in H.264/AVC. : ASICON 2005: 2005 6th International Conference on ASIC, Proceedings (pp. 262-265). [1611300] (ASICON 2005: 2005 6th International Conference on ASIC, Proceedings; 巻数 1).