Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. An FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2k butterfly units (BUs) could be scheduled to work in parallel on n=2sdata (k=0, 1, ..., s-1). Because no inter stage data transfer is required, memory consumption is reduced to 1/3 of the original algorithm. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. An 18-bit word-length 1024-point FFT architecture with 4 BUs is given to demonstrate this mapping algorithm. The design is implemented with TSMC 0.18μm CMOS technology. The core area is 2.99×1.12mm2 and clock frequency is 326MHz in typical condition (1.8V, 25°C). This processor could complete 1024 FFT calculation in 7.839μs.
|出版ステータス||Published - 2005 12 29|
|イベント||2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States|
継続期間: 2005 4 17 → 2005 4 19
|Conference||2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05|
|Period||05/4/17 → 05/4/19|
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