A wide lock-in range PLL using self-calibrating technique for processors

Jingo Nakanishi, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara

研究成果: Conference contribution

抄録

A wide lock-in range PLL using a self-calibrating technique is proposed. This technique realizes a wide lock-in range and good jitter characteristics by performing the digital calibration at the start of the operation. However, self-calibration with a large number of digital control steps increases the test costs and circuit scale. In this paper, by estimating the margin for self-calibrating operation, the minimum number of digital control steps was determined. A PLL with a low test cost, a wide lock-in range and low jitter was designed and implemented using a 0.15 μm 1.5 V CMOS process. The measured PLL lock-in range is 80 MHz - 630 MHz with four digital calibration steps. The peak-to-peak jitter at 380 MHz is 100 ps.

本文言語English
ホスト出版物のタイトル2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
出版社IEEE Computer Society
ページ285-288
ページ数4
ISBN(印刷版)0780391624, 9780780391628
DOI
出版ステータスPublished - 2005 1 1
外部発表はい
イベント1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China
継続期間: 2005 11 12005 11 3

出版物シリーズ

名前2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Other

Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan, Province of China
CityHsinchu
Period05/11/105/11/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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