A wide lock-in range PLL using a self-calibrating technique is proposed. This technique realizes a wide lock-in range and good jitter characteristics by performing the digital calibration at the start of the operation. However, self-calibration with a large number of digital control steps increases the test costs and circuit scale. In this paper, by estimating the margin for self-calibrating operation, the minimum number of digital control steps was determined. A PLL with a low test cost, a wide lock-in range and low jitter was designed and implemented using a 0.15 μm 1.5 V CMOS process. The measured PLL lock-in range is 80 MHz - 630 MHz with four digital calibration steps. The peak-to-peak jitter at 380 MHz is 100 ps.