Accelerating convolutional neural network inference based on a reconfigurable sliced systolic array

Yixuan Zeng, Heming Sun, Jiro Katto, Yibo Fan

研究成果: Conference contribution

抄録

Convolutional neural networks (CNNs) have achieved great successes on many computer vision tasks, such as image recognition, video processing, and target detection. In recent years, many hardware designs have been devoted to accelerating CNN inference. In order to further speed up CNN inference and reduce data waste, this work proposed a reconfigurable sliced systolic array: 1) Depending on the number of network nodes in each layer, the slice mode could be dynamically configured to achieve high throughput and resource utilization. 2) To take full advantage of convolution reuse and weight reuse, this work designed a tile-column sliding (TCS) processing dataflow. 3) A four-stage for loop algorithm was employed, which divides the CNN calculation into several parts based on the input nodes and output nodes. The entire CNN inference is carried out using integer-only arithmetic originated from TensorLite. Experimental results prove that these strategies lead to significant improvement in inference performance and energy efficiency.

本文言語English
ホスト出版物のタイトル2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728192017
DOI
出版ステータスPublished - 2021
イベント53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of
継続期間: 2021 5 222021 5 28

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
2021-May
ISSN(印刷版)0271-4310

Conference

Conference53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
国/地域Korea, Republic of
CityDaegu
Period21/5/2221/5/28

ASJC Scopus subject areas

  • 電子工学および電気工学

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