抄録
The existing System on Chip (SoC) design will soon become a critical bottle neck in chip performance with its inability to scale its communication network effectively with decreasing feature sizes and increasing number of transistors. The Network on Chip (NoC) has been recognized as the next evolutionary step to tackle these issues by using an intelligent and common communication network between all the different components within chip. In this paper we propose a new routing algorithm that uses a combination of a fully adaptive and partial adaptive routing algorithm called Adaptive Look Ahead algorithm. The algorithm decides next two hops within one node to allow quick packet transfer in next node, hence the algorithm only periodically calculates the packets route along the minimal path. Experimental results show that our proposed algorithm has lower latency and higher throughput than existing benchmarks.
本文言語 | English |
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ホスト出版物のタイトル | Souvenir of the 2015 IEEE International Advance Computing Conference, IACC 2015 |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ページ | 299-302 |
ページ数 | 4 |
ISBN(印刷版) | 9781479980475 |
DOI | |
出版ステータス | Published - 2015 7 10 |
イベント | 2015 5th IEEE International Advance Computing Conference, IACC 2015 - Bangalore, India 継続期間: 2015 6 12 → 2015 6 13 |
Other
Other | 2015 5th IEEE International Advance Computing Conference, IACC 2015 |
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Country | India |
City | Bangalore |
Period | 15/6/12 → 15/6/13 |
ASJC Scopus subject areas
- Computer Networks and Communications
- Computational Theory and Mathematics
- Computer Science Applications
- Hardware and Architecture
- Signal Processing
- Modelling and Simulation