TY - JOUR
T1 - Adaptive sub-sampling based reconfigurable SAD tree architecture for HDTV application
AU - Huang, Yiqing
AU - Liu, Qin
AU - Goto, Satoshi
AU - Ikenaga, Takeshi
PY - 2009/11
Y1 - 2009/11
N2 - This paper presents a reconfigurable SAD Tree (RSADT) architecture based on adaptive sub-sampling algorithm for HDTV application. Firstly, to obtain the the feature of HDTV picture, pixel difference analysis is applied on each macroblock (MB). Three hardware friendly sub-sampling patterns are selected adaptively to release complexity of homogeneous MB and keep video quality for texture MB. Secondly, since two pipeline stages are inserted, the whole clock speed of RSADT structure is enhanced. Thirdly, to solve data reuse and hardware utilization problem of adaptive algorithm, the RSADT structure adopts pixel data organization in both memory and architecture level, which leads to full data reuse and hardware utilization. Additionally, a cross reuse structure is proposed to efficiently generate 16 pixel scaled configurable SAD (sum of absolute difference). Experimental results show that, our RSADT architecture can averagely save 61.71% processing cycles for integer motion estimation engine and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency of our design is 208 MHz under TSMC 0.18 μm technology in worst work conditions(1.62 V, 125°C). Furthermore, the proposed algorithm and reconfigurable structure are favorable to power aware real-time encoding system.
AB - This paper presents a reconfigurable SAD Tree (RSADT) architecture based on adaptive sub-sampling algorithm for HDTV application. Firstly, to obtain the the feature of HDTV picture, pixel difference analysis is applied on each macroblock (MB). Three hardware friendly sub-sampling patterns are selected adaptively to release complexity of homogeneous MB and keep video quality for texture MB. Secondly, since two pipeline stages are inserted, the whole clock speed of RSADT structure is enhanced. Thirdly, to solve data reuse and hardware utilization problem of adaptive algorithm, the RSADT structure adopts pixel data organization in both memory and architecture level, which leads to full data reuse and hardware utilization. Additionally, a cross reuse structure is proposed to efficiently generate 16 pixel scaled configurable SAD (sum of absolute difference). Experimental results show that, our RSADT architecture can averagely save 61.71% processing cycles for integer motion estimation engine and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency of our design is 208 MHz under TSMC 0.18 μm technology in worst work conditions(1.62 V, 125°C). Furthermore, the proposed algorithm and reconfigurable structure are favorable to power aware real-time encoding system.
KW - H.264/AVC
KW - HDTV
KW - Reconfigurable architecture
KW - SAD tree
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=77952645553&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77952645553&partnerID=8YFLogxK
U2 - 10.1587/transfun.E92.A.2819
DO - 10.1587/transfun.E92.A.2819
M3 - Article
AN - SCOPUS:77952645553
SN - 0916-8508
VL - E92-A
SP - 2819
EP - 2829
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 11
ER -