An 18.5ns 128Mb SOI DRAM with a floating body cell

Takashi Ohsawa; Katsuyuki Fujita; Kosuke Hatsuda; Tomoki Higashi; Mutsuo Morikado; Yoshihiro Minami; Tomoaki Shino; Hiroomi Nakajima; Kazumi Inoh; Takeshi Hamamoto; Shigeyoshi Watanabe

An 18.5ns 128Mb SOI DRAM with a floating body cell

Takashi Ohsawa^*, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe

^*この研究の対応する著者

研究成果: Conference article › 査読

1 被引用数 (Scopus)

抄録

A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out.

本文言語	English
論文番号	25.1
ページ（範囲）	376-377+694
ジャーナル	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
巻	48
出版ステータス	Published - 2005 12 6
外部発表	はい
イベント	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States 継続期間: 2005 2 6 → 2005 2 10

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

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引用スタイル

An 18.5ns 128Mb SOI DRAM with a floating body cell. / Ohsawa, Takashi; Fujita, Katsuyuki; Hatsuda, Kosuke; Higashi, Tomoki; Morikado, Mutsuo; Minami, Yoshihiro; Shino, Tomoaki; Nakajima, Hiroomi; Inoh, Kazumi; Hamamoto, Takeshi; Watanabe, Shigeyoshi.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 48, 25.1, 06.12.2005, p. 376-377+694.

研究成果: Conference article › 査読

Ohsawa, Takashi ; Fujita, Katsuyuki ; Hatsuda, Kosuke ; Higashi, Tomoki ; Morikado, Mutsuo ; Minami, Yoshihiro ; Shino, Tomoaki ; Nakajima, Hiroomi ; Inoh, Kazumi ; Hamamoto, Takeshi ; Watanabe, Shigeyoshi. / An 18.5ns 128Mb SOI DRAM with a floating body cell. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2005 ; Vol. 48. pp. 376-377+694.

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AU - Minami, Yoshihiro

AU - Shino, Tomoaki

AU - Nakajima, Hiroomi

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AU - Hamamoto, Takeshi

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An 18.5ns 128Mb SOI DRAM with a floating body cell

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