抄録
An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 1147-1152 |
| ページ数 | 6 |
| ジャーナル | IEEE Journal of Solid-State Circuits |
| 巻 | 25 |
| 発行部数 | 5 |
| DOI | |
| 出版物ステータス | Published - 1990 10 |
| 外部発表 | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
これを引用
An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. / Seki, Koichi; Kume, Hitoshi; Ohji, Yuzuru; Kobayashi, Takashi; Hiraiwa, Atsushi; Nishida, Takashi; Wada, Takeshi; Komori, Kazuhiro; Izawa, Kazuto; Nishimoto, Toshiaki; Kubota, Yasuroh; Shohji, Kazuyoshi.
：: IEEE Journal of Solid-State Circuits, 巻 25, 番号 5, 10.1990, p. 1147-1152.研究成果: Article
}
TY - JOUR
T1 - An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller
AU - Seki, Koichi
AU - Kume, Hitoshi
AU - Ohji, Yuzuru
AU - Kobayashi, Takashi
AU - Hiraiwa, Atsushi
AU - Nishida, Takashi
AU - Wada, Takeshi
AU - Komori, Kazuhiro
AU - Izawa, Kazuto
AU - Nishimoto, Toshiaki
AU - Kubota, Yasuroh
AU - Shohji, Kazuyoshi
PY - 1990/10
Y1 - 1990/10
N2 - An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.
AB - An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.
UR - http://www.scopus.com/inward/record.url?scp=0025503362&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0025503362&partnerID=8YFLogxK
U2 - 10.1109/4.62136
DO - 10.1109/4.62136
M3 - Article
AN - SCOPUS:0025503362
VL - 25
SP - 1147
EP - 1152
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 5
ER -