抄録
An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.
本文言語 | English |
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ページ(範囲) | 1147-1152 |
ページ数 | 6 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 25 |
号 | 5 |
DOI | |
出版ステータス | Published - 1990 10月 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学