An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

研究成果: Conference contribution

34 被引用数 (Scopus)

抄録

A 104.8mm2 90nm CMOS 600MHz SoC integrates 8 processor cores and 8 user RAMs in 17 separate power domains and delivers 33.6GFLOPS. An automatic parallelizing compiler assigns tasks to each CPU and controls its power mode including power supply in accordance with its processing load and status. The compiler also uses barrier registers to achieve fast and accurate CPU synchronization.

本文言語English
ホスト出版物のタイトル2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
出版社Institute of Electrical and Electronics Engineers Inc.
ページ89-91
ページ数3
ISBN(印刷版)9781424420100
DOI
出版ステータスPublished - 2008
イベント2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States
継続期間: 2008 2 32008 2 7

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
51
ISSN(印刷版)0193-6530

Conference

Conference2008 IEEE International Solid State Circuits Conference, ISSCC
国/地域United States
CitySan Francisco, CA
Period08/2/308/2/7

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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