An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture

Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko

研究成果: Article

103 引用 (Scopus)

抜粋

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RB number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RB number into the corresponding NB number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54 × 54-bit multiplier is designed with this architecture. It is fabricated by 0.5 μm CMOS with triple level metal technology. The active area size is 3.05 × 3.08 mm2 and the number of transistors is 78,800. This is the smallest number for all 54 × 54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54 × 54-bit multipliers with 0.5-μm CMOS.

元の言語English
ページ(範囲)773-782
ページ数10
ジャーナルIEEE Journal of Solid-State Circuits
31
発行部数6
DOI
出版物ステータスPublished - 1996 6 1
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用