An adaptive test for parametric faults based on statistical timing information

Michihiro Shintani*, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu

*この研究の対応する著者

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

The continuing miniaturization of LSI dimension is causing the increase of process-Related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

本文言語English
ホスト出版物のタイトルProceedings of the 18th Asian Test Symposium, ATS 2009
ページ151-156
ページ数6
DOI
出版ステータスPublished - 2009
外部発表はい
イベント18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan, Province of China
継続期間: 2009 11月 232009 11月 26

出版物シリーズ

名前Proceedings of the Asian Test Symposium
ISSN(印刷版)1081-7735

Conference

Conference18th Asian Test Symposium, ATS 2009
国/地域Taiwan, Province of China
CityTaichung
Period09/11/2309/11/26

ASJC Scopus subject areas

  • 電子工学および電気工学

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