An adaptive width data cache for low power design

Jiongyao Ye*, Takahiro Watanabe

*この研究の対応する著者

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. The storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes an Adaptive Width Data Cache (AWDC) which exploits the popularity of NWV stored in the cache. In AWDC, the cache data array is divided into several data arrays to adapt different data width to access/store. Its purpose is shutting off corresponding unused high arrays to reduce its dynamic and static power consumption. AWDC achieves low power consumption only by the modification of the high-bit SRAM unit almost without any additional hardware, and does not affect cache performance. Experimental results employing SPEC 2000 benchmarks show that our proposed AWDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

本文言語English
ホスト出版物のタイトル2009 International SoC Design Conference, ISOCC 2009
ページ488-491
ページ数4
DOI
出版ステータスPublished - 2009 12 1
イベント2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
継続期間: 2009 11 222009 11 24

出版物シリーズ

名前2009 International SoC Design Conference, ISOCC 2009

Conference

Conference2009 International SoC Design Conference, ISOCC 2009
国/地域Korea, Republic of
CityBusan
Period09/11/2209/11/24

ASJC Scopus subject areas

  • 電子工学および電気工学

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