An adder-segmentation-based FIR for high speed signal processing

研究成果: Conference contribution

1 引用 (Scopus)

抜粋

An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.

元の言語English
ホスト出版物のタイトルProceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
編集者Fan Ye, Ting-Ao Tang
出版者IEEE Computer Society
ISBN(電子版)9781728107356
DOI
出版物ステータスPublished - 2019 10
イベント13th IEEE International Conference on ASIC, ASICON 2019 - Chongqing, China
継続期間: 2019 10 292019 11 1

出版物シリーズ

名前Proceedings of International Conference on ASIC
ISSN(印刷物)2162-7541
ISSN(電子版)2162-755X

Conference

Conference13th IEEE International Conference on ASIC, ASICON 2019
China
Chongqing
期間19/10/2919/11/1

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Ye, J., Yanagisawa, M., & Shi, Y. (2019). An adder-segmentation-based FIR for high speed signal processing. : F. Ye, & T-A. Tang (版), Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019 [8983612] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON47005.2019.8983612