An advanced model for calculating the effective capacitance considering input waveform effect

Minglu Jiang*, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

*この研究の対応する著者

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    In deep submicron designs, predicting gate delays is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect load. Conventionally, the input-signal is assumed as ramp waveform. However, the input waveform is also the output of CMOS gates with interconnect wires. Thus the simple assumption as a ramp signal results in significant influence on the delay calculating. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and interconnect wire load, where the nonlinear influence of input waveform is modeled as one part of effective capacitance of capacitive load to compute the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

    本文言語English
    ホスト出版物のタイトル2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
    ページ1088-1092
    ページ数5
    DOI
    出版ステータスPublished - 2008
    イベント2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province
    継続期間: 2008 5 252008 5 27

    Other

    Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
    CityXiamen, Fujian Province
    Period08/5/2508/5/27

    ASJC Scopus subject areas

    • コンピュータ ネットワークおよび通信
    • ハードウェアとアーキテクチャ
    • 制御およびシステム工学
    • 電子工学および電気工学

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