An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Y. Miyaoka, J. Choi, N. Togawa, M. Yanagisawa, T. Ohtsuki

研究成果: Conference contribution

抄録

The authors consider the synthesis of a processor core with SIMD instructions by a hardware/software cosynthesis system. The system is required to configure functional units executing SIMD instructions and obtain the area and delay of the functional units to evaluate the synthesized processor core. This paper proposes a hardware unit generation algorithm for a hardware/software cosynthesis system of processors with SIMD instructions. Given a set of instructions to be executed by a hardware unit and constraints for area and delay of the hardware unit, the proposed algorithm extracts a set of subfunctions to be required by the hardware unit and generates more than one architecture candidates for the hardware unit. The algorithm also outputs the estimated area and delay of each of the generated hardware units. The execution time of the proposed algorithm is very short and thus it can be easily incorporated into the processor core synthesis system. Experimental results demonstrate effectiveness and efficiency of the algorithm.

本文言語English
ホスト出版物のタイトルProceedings - APCCAS 2002
ホスト出版物のサブタイトルAsia-Pacific Conference on Circuits and Systems
出版社Institute of Electrical and Electronics Engineers Inc.
ページ171-176
ページ数6
ISBN(電子版)0780376900
DOI
出版ステータスPublished - 2002
イベントAsia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia
継続期間: 2002 10月 282002 10月 31

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
1

Other

OtherAsia-Pacific Conference on Circuits and Systems, APCCAS 2002
国/地域Indonesia
CityDenpasar, Bali
Period02/10/2802/10/31

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル