Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. In this method, the transmitter divides of the message by an agreed-upon polynomial called the generator and concatenates the calculated residue to the message. The receiver divides what it receives by the generator again. A zero residue indicates error-free transmission and a nonzero residue is interpreted as an error. These calculations are traditionally performed using serial circuits called LFSR especially in serial communications such as the case of the Ethernet protocol. But in parallel communications such as USB, and also integrity checking applications, this method is not efficient enough. In this paper, a new parallel algorithm for parallel CRC calculation is proposed and evaluated. The proposed algorithm exploits mathematical properties of a special family of generator polynomials named OZZ (One-Zero-Zero) polynomials. In this approach, we feedbacks are eliminated and pipelined calculations are used to obtain 32-bit CRC in the SMIC 0.35/im CMOS technology.