TY - GEN

T1 - An approach to exploiting proper multiples of the generator polynomial in parallel CRC computation

AU - Mehrabian, Mohammad Reza

AU - Mozafari, Saadat Pour

AU - Zolfaghari, Behrouz

PY - 2012

Y1 - 2012

N2 - Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. In this method, the transmitter divides of the message by an agreed-upon polynomial called the generator and concatenates the calculated residue to the message. The receiver divides what it receives by the generator again. A zero residue indicates error-free transmission and a nonzero residue is interpreted as an error. These calculations are traditionally performed using serial circuits called LFSR especially in serial communications such as the case of the Ethernet protocol. But in parallel communications such as USB, and also integrity checking applications, this method is not efficient enough. In this paper, a new parallel algorithm for parallel CRC calculation is proposed and evaluated. The proposed algorithm exploits mathematical properties of a special family of generator polynomials named OZZ (One-Zero-Zero) polynomials. In this approach, we feedbacks are eliminated and pipelined calculations are used to obtain 32-bit CRC in the SMIC 0.35/im CMOS technology.

AB - Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. In this method, the transmitter divides of the message by an agreed-upon polynomial called the generator and concatenates the calculated residue to the message. The receiver divides what it receives by the generator again. A zero residue indicates error-free transmission and a nonzero residue is interpreted as an error. These calculations are traditionally performed using serial circuits called LFSR especially in serial communications such as the case of the Ethernet protocol. But in parallel communications such as USB, and also integrity checking applications, this method is not efficient enough. In this paper, a new parallel algorithm for parallel CRC calculation is proposed and evaluated. The proposed algorithm exploits mathematical properties of a special family of generator polynomials named OZZ (One-Zero-Zero) polynomials. In this approach, we feedbacks are eliminated and pipelined calculations are used to obtain 32-bit CRC in the SMIC 0.35/im CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=84867085080&partnerID=8YFLogxK

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U2 - 10.1109/CSAE.2012.6272670

DO - 10.1109/CSAE.2012.6272670

M3 - Conference contribution

AN - SCOPUS:84867085080

SN - 9781467300865

T3 - CSAE 2012 - Proceedings, 2012 IEEE International Conference on Computer Science and Automation Engineering

SP - 614

EP - 617

BT - CSAE 2012 - Proceedings, 2012 IEEE International Conference on Computer Science and Automation Engineering

T2 - 2012 IEEE International Conference on Computer Science and Automation Engineering, CSAE 2012

Y2 - 25 May 2012 through 27 May 2012

ER -