An area-effective datapath architecture for embedded microprocessors and scalable systems

Toshiaki Inoue*, Takashi Manabe, Sunao Torii, Satoshi Masushita, Masato Edahiro, Naoki Nishi, Masakazu Yamashina

*この研究の対応する著者

研究成果: Article査読

抄録

We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-μm 5-metal CMOS technology.

本文言語English
ページ(範囲)1014-1020
ページ数7
ジャーナルIEICE Transactions on Electronics
E84-C
8
出版ステータスPublished - 2001 8月
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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