TY - JOUR
T1 - An area-effective datapath architecture for embedded microprocessors and scalable systems
AU - Inoue, Toshiaki
AU - Manabe, Takashi
AU - Torii, Sunao
AU - Masushita, Satoshi
AU - Edahiro, Masato
AU - Nishi, Naoki
AU - Yamashina, Masakazu
PY - 2001/8
Y1 - 2001/8
N2 - We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-μm 5-metal CMOS technology.
AB - We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-μm 5-metal CMOS technology.
KW - Area-efficiency
KW - Embedded microprocessor
KW - Multiplier
KW - Onchip multiprocessor
KW - SIMD
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M3 - Article
AN - SCOPUS:0035421285
VL - E84-C
SP - 1014
EP - 1020
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 8
ER -