An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder

Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

This paper presents a new VLSI architecture for HEVC inverse discrete cosine transform (TDCT). Compared to prior arts, this work reduces hardware cost by 1) reducing computational logic of 1-D IDCTs with a reordered parallel-in serial-out (RPISO) scheme that shares the inputs of the butterfly structure, and 2) reducing the area of the transpose buffer with a cyclic memory organization that achieves 100% I/O utilization of the SRAMs. In the implementation of a unified 4/8/16/32-point IDCT, the proposed schemes demonstrate 35% and 62% reduction of logic and memory costs, respectively. The IDCT implementation can support real-time decoding of 4K×2K 60fps video with a total hardware cost of 357,250um2 on 2-D IDCT and 80,988um2 on transpose memory in 90nm process.

本文言語English
ホスト出版物のタイトル2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ197-200
ページ数4
ISBN(電子版)9781479961399
DOI
出版ステータスPublished - 2015 2 27
イベント2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014 - Valletta, Malta
継続期間: 2014 12 72014 12 10

出版物シリーズ

名前2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014

Other

Other2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014
国/地域Malta
CityValletta
Period14/12/714/12/10

ASJC Scopus subject areas

  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • コンピュータ ビジョンおよびパターン認識

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