An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

This paper proposes an area/time optimizing algorithm in high-level synthesis for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.

本文言語English
ホスト出版物のタイトルProceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
ページ309-312
ページ数4
DOI
出版ステータスPublished - 2000
イベント2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama, Japan
継続期間: 2000 1月 252000 1月 28

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
国/地域Japan
CityYokohama
Period00/1/2500/1/28

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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