An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications

Leona Okamura, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Tsutomu Yoshihara

    研究成果: Conference contribution

    3 被引用数 (Scopus)

    抄録

    SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

    本文言語English
    ホスト出版物のタイトル2006 International Symposium on Communications and Information Technologies, ISCIT
    ページ771-774
    ページ数4
    DOI
    出版ステータスPublished - 2006
    イベント2006 International Symposium on Communications and Information Technologies, ISCIT - Bangkok
    継続期間: 2006 10 182006 10 20

    Other

    Other2006 International Symposium on Communications and Information Technologies, ISCIT
    CityBangkok
    Period06/10/1806/10/20

    ASJC Scopus subject areas

    • コンピュータ ネットワークおよび通信
    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

    フィンガープリント

    「An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル