An effecient level-shifter floorplanning method for multi-voltage design

Xiaolin Zhang, Zhi Lin, Song Chen, Takeshi Yoshimura

研究成果: Conference contribution

6 引用 (Scopus)

抜粋

Nowdays, Low-power design, especially Multi-voltage design becomes a popular and efficient way to reduce both dynamic power and static power. In this paper, we propose an efficient method of level-shifter floorplanning for a given multi-voltage design. This method is a two stage optimization method. First, for a given voltage island and its sequence pair representation, we greedily pre-place level-shifters into white-spaces of multi-voltage island based sequence-pair representation. Then, we employ a modified IARFP [1] algorithm to re-optimize the positions of level-shifters. Experimental results show that, the proposed two stage level-shifter floorplanner is efficient for post multi-voltage island optimization.

元の言語English
ホスト出版物のタイトルProceedings of International Conference on ASIC
ページ421-424
ページ数4
DOI
出版物ステータスPublished - 2011
イベント2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
継続期間: 2011 10 252011 10 28

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
Xiamen
期間11/10/2511/10/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Zhang, X., Lin, Z., Chen, S., & Yoshimura, T. (2011). An effecient level-shifter floorplanning method for multi-voltage design. : Proceedings of International Conference on ASIC (pp. 421-424). [6157211] https://doi.org/10.1109/ASICON.2011.6157211