An effective model of the overshooting effect for multiple-input gates in nanometer technologies

Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue

    研究成果査読

    抄録

    With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multipleinput gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32 nm PTM model.

    本文言語English
    ページ(範囲)1059-1074
    ページ数16
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E97-A
    5
    DOI
    出版ステータスPublished - 2014

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • コンピュータ グラフィックスおよびコンピュータ支援設計
    • 応用数学
    • 信号処理

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