An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead

Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

    研究成果: Article

    3 引用 (Scopus)

    抄録

    As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

    元の言語English
    ページ（範囲）1406-1418
    ページ数13
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    巻E98A
    発行部数7
    DOI
    出版物ステータスPublished - 2015 7 1

    Fingerprint

    Prediction Error
    Insertion
    Timing
    Networks (circuits)
    Checkpoint
    Min-cut
    Path
    Error correction
    Error Correction
    Count
    Monitoring
    Minimise
    Predict
    Output

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    これを引用

    An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead. / Yoshida, Shinnosuke; Shi, Youhua; Yanagisawa, Masao; Togawa, Nozomu.

    ：: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E98A, 番号 7, 01.07.2015, p. 1406-1418.

    研究成果: Article

    Yoshida, S, Shi, Y, Yanagisawa, M & Togawa, N 2015, 'An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead', IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻. E98A, 番号 7, pp. 1406-1418. https://doi.org/10.1587/transfun.E98.A.1406
    Yoshida S, Shi Y, Yanagisawa M, Togawa N. An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2015 7 1;E98A(7):1406-1418. https://doi.org/10.1587/transfun.E98.A.1406
    Yoshida, Shinnosuke ; Shi, Youhua ; Yanagisawa, Masao ; Togawa, Nozomu. / An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead. ：: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2015 ; 巻 E98A, 番号 7. pp. 1406-1418.
    @article{dc32e974b65e4c62804f05ed2452920e,
    title = "An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead",
    abstract = "As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.",
    keywords = "Delay variation, Overclocking, Robust design, Timing-error prediction",
    author = "Shinnosuke Yoshida and Youhua Shi and Masao Yanagisawa and Nozomu Togawa",
    year = "2015",
    month = "7",
    day = "1",
    doi = "10.1587/transfun.E98.A.1406",
    language = "English",
    volume = "E98A",
    pages = "1406--1418",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "7",

    }

    TY - JOUR

    T1 - An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead

    AU - Yoshida, Shinnosuke

    AU - Shi, Youhua

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2015/7/1

    Y1 - 2015/7/1

    N2 - As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

    AB - As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

    KW - Delay variation

    KW - Overclocking

    KW - Robust design

    KW - Timing-error prediction

    UR - http://www.scopus.com/inward/record.url?scp=84937622478&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84937622478&partnerID=8YFLogxK

    U2 - 10.1587/transfun.E98.A.1406

    DO - 10.1587/transfun.E98.A.1406

    M3 - Article

    AN - SCOPUS:84937622478

    VL - E98A

    SP - 1406

    EP - 1418

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 7

    ER -

    文献にアクセス