An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Lingfeng Li, Satoshi Goto, Takeshi Ikenaga

研究成果: Conference contribution

21 引用 (Scopus)

抜粋

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

元の言語English
ホスト出版物のタイトルProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
ページ623-626
ページ数4
出版物ステータスPublished - 2005 12 1
イベント2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
継続期間: 2005 1 182005 1 21

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
1

Conference

Conference2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
China
Shanghai
期間05/1/1805/1/21

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • これを引用

    Li, L., Goto, S., & Ikenaga, T. (2005). An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. : Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 623-626). [1466238] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 1).