The application of 3D Networks-on-chip (NoCs) has been proved to be an effective solution to the global communication of 3D IC integration, while the design of NoC topologies has played a critical role to increase interconnection performance. In this work, we propose a new procedure for designing application specific irregular 3D NoC topologies which achieve significant performance improvement. The objective is to improve both communication latency and power consumption under several 3D constraints. We propose a two-stage design model based on a series of efficient algorithms to explore the optimized topology in a large scale searching space. Numerical experimental results show that the topologies by our design algorithm achieve more performance improvement (about 31.5%) than the classical topologies and the proposed algorithm also proves to be a time efficient method for exploration in the large solution space.