An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power

Xin Jiang, Ran Zhang, Takahiro Watanabe

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The application of 3D Networks-on-chip (NoCs) has been proved to be an effective solution to the global communication of 3D IC integration, while the design of NoC topologies has played a critical role to increase interconnection performance. In this work, we propose a new procedure for designing application specific irregular 3D NoC topologies which achieve significant performance improvement. The objective is to improve both communication latency and power consumption under several 3D constraints. We propose a two-stage design model based on a series of efficient algorithms to explore the optimized topology in a large scale searching space. Numerical experimental results show that the topologies by our design algorithm achieve more performance improvement (about 31.5%) than the classical topologies and the proposed algorithm also proves to be a time efficient method for exploration in the large solution space.

本文言語English
ホスト出版物のタイトルProceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
ページ535-538
ページ数4
DOI
出版ステータスPublished - 2011 12 1
イベント2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China
継続期間: 2011 10 252011 10 28

出版物シリーズ

名前Proceedings of International Conference on ASIC
ISSN(印刷版)2162-7541
ISSN(電子版)2162-755X

Conference

Conference2011 IEEE 9th International Conference on ASIC, ASICON 2011
国/地域China
CityXiamen
Period11/10/2511/10/28

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル