In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 μm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.
|ジャーナル||IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences|
|出版ステータス||Published - 2012 2|
ASJC Scopus subject areas
- コンピュータ グラフィックスおよびコンピュータ支援設計