An efficient dual charge pump circuit using charge sharing clock scheme

Mengshu Huang*, Yimeng Zhang, Tsutomu Yoshihara

*この研究の対応する著者

    研究成果: Article査読

    抄録

    In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 μm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

    本文言語English
    ページ(範囲)439-446
    ページ数8
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E95-A
    2
    DOI
    出版ステータスPublished - 2012 2

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • コンピュータ グラフィックスおよびコンピュータ支援設計
    • 応用数学
    • 信号処理

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