An efficient hardware routing algorithms for NoC

Yiping Dong, Zhen Lin, Takahiro Watanabe

研究成果: Conference contribution

3 引用 (Scopus)

抜粋

Networks on Chip (NoC) has been widely discussed for its smart structure and high performance. Routing algorithms significantly influence design cost and system performance of NoC. In this paper, a new hardware method called FinalDestination-Tag (FDT) is proposed to improve the original Destination-Tag (DT) method for implementing different routing algorithms. Compared with the DT method, the proposed FDT method could reduce the header size of the packet. We evaluate NoC with this proposed method in terms of circuit resource, average latency, max latency, average throughput and power consumption. The results indicate that the proposed method is effective in increasing throughput and reducing circuit resource, latency and power consumption for NoC.

元の言語English
ホスト出版物のタイトルTENCON 2010 - 2010 IEEE Region 10 Conference
ページ1525-1530
ページ数6
DOI
出版物ステータスPublished - 2010 12 1
イベント2010 IEEE Region 10 Conference, TENCON 2010 - Fukuoka, Japan
継続期間: 2010 11 212010 11 24

出版物シリーズ

名前IEEE Region 10 Annual International Conference, Proceedings/TENCON

Other

Other2010 IEEE Region 10 Conference, TENCON 2010
Japan
Fukuoka
期間10/11/2110/11/24

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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  • これを引用

    Dong, Y., Lin, Z., & Watanabe, T. (2010). An efficient hardware routing algorithms for NoC. : TENCON 2010 - 2010 IEEE Region 10 Conference (pp. 1525-1530). [5686149] (IEEE Region 10 Annual International Conference, Proceedings/TENCON). https://doi.org/10.1109/TENCON.2010.5686149